Semiconductor diode and method for producing the same

ABSTRACT

A semiconductor arrangement and a method for manufacturing the semiconductor arrangement are provided, which arrangement and method allow an improvement in the current-carrying capacity for given chip dimensions. The semiconductor arrangement includes trenches introduced in the interior of the chip, which trenches reduce power loss and improve the heat dissipation of the chip, as well as reduce the forward voltage of diode.

FIELD OF THE INVENTION

The present invention relates to a semiconductor arrangement and amethod for manufacturing the semiconductor arrangement.

BACKGROUND OF THE INVENTION

German Patent document No. P 4320780.4 describes a semiconductor diodehaving a first layer made of two partial layers, and a second layerwhich is situated on the first partial layer.

SUMMARY OF THE INVENTION

The present invention's semiconductor arrangement and method formanufacturing the semiconductor arrangement has the advantage ofproviding diodes having an increased maximum permissible power and lessforward voltage for a given chip surface, in a manner suitable forlarge-scale mass production, without a large amount of additionalengineering expense. This is particularly advantageous when a maximumpreselected chip surface area should not be exceeded in order to savechip surface, and when the size of the contact socket used to contactthe semiconductor arrangement should not exceed a certain magnitude, inorder to avoid paying for an increased current-carrying capacity ofdiodes particularly used in a motor-vehicle rectifier system, with anincreased volume of the entire rectifier system. The present inventionfacilitates, given a constant surface area of the silicon

DETAILED DESCRIPTION

FIG. 1a shows a cross-sectional side view of a semiconductor chip 7,which is in the form of a diode. Chip 7 has a first semiconductor layerwhich is made of a first partial layer 2, a second partial layer 3, anda third partial layer 4. The doping of n-doped partial layer 2 is on theorder of 10¹⁸ cm⁻³. Partial layer 3 is n-doped to a concentration ofapproximately 10¹⁴ cm⁻³, and partial layer 4 is doped toan—concentration of approximately 10²⁰ cm⁻³. Two trenches 10 areintroduced into partial layer 2, which trenches extend into partiallayer 3. These trenches 10 are situated in inner region 13 of chip 7.Edge regions 12 of the chip have a bevel 11, which extends into partiallayer 3 as do trenches 10. Deposited onto first partial layer 2, bothinto trenches 10 and in bevel 11, is a second layer 20, whose regions intrenches 10 and bevels 11 are designated as continuation regions 23 andfurther continuation regions 24 of second layer 20, respectively. Secondlayer 20 is p-doped and has a doping on the order of 10²⁰ cm⁻³. Thewafer topside, which is covered by layer 20, and the wafer bottom side,which is formed by layer 4, are provided with metallic coatings 22 and21, respectively. FIG. 1b shows a plan view of the chip 7 shown in FIG.1a. The top of chip 7 is covered by metallic coating 22. As a result ofthe trenches 10 that are introduced, this metallic coating 22 has apattern characterized by corresponding depressions.

The p-n junction region of the diode is formed by p-doped layer 20 andn-doped layers 2 and 3 of FIG. 1a. As a result of the trenches 10 thatare introduced, continuation regions 23 in interior 13 of chip 7 form ap-n junction with second partial layer 3. These regions lead to areduction in the forward voltage of the diode, with metallic coating 22being used as the anode and metallic coating 21 being used as thecathode. The four grooves in the interior of chip 7 (cf. FIG. 1b) allowthe electrical load to be increased by over 12% in comparison with anidentically constructed diode not having grooves in the interior. Inother words, a diode that can withstand, for example, a 65 A load may beconverted to a diode having a maximum load of 75 A. An 80 A diodebecomes a 90 A diode. The forward voltage may be reduced byapproximately 60 mV (measured at a 100 A load). The four additionalgrooves or trenches in the interior of chip 7 also result in the chipbeing soldered more effectively and free of bubbles, i.e. the socket andlead wire are attached to the diode chip in an improved manner. Inaddition, the grooves filled with solder during this soldering procedure(not shown in the figure) ensure that the chip cools in an improvedmanner, since the solder in the grooves, which then completely fills thegrooves, thermally couples the chip in an intensive manner, to a metalbase used as a heat sink.

FIG. 1b shows an exemplary embodiment of a chip 7, i.e., a square chip.However, not only are squares possible, but also other surfaces that aredefined by straight edges (e.g. a hexagon or an octagon) and haveadditional, corresponding internal grooves parallel to the edges.

FIG. 2 shows a semiconductor wafer having a first partial layer 2, asecond partial layer 3, and a third partial layer 4, which wafer is usedin producing the semiconductor arrangement of the present invention. Allthree partial layers are n-doped. The starting point for manufacturingthis sequence of layers is a weakly n-doped wafer, whose dopantconcentration corresponds to the dopant concentration of partial layer3. N-dopant, e.g. phosphorus, is then introduced onto and diffused intothe topside and bottom side, using film diffusion. A layer, whose dopantconcentration corresponds to partial layer 2, is consequently formed onthe topside, and a layer, whose dopant concentration corresponds topartial layer 4, is formed on the bottom side. In this context, thedopant concentration of the layers is determined by the dopantconcentration of the films.

The manufacture of such a layer sequence is already known from GermanPatent document No. P 4320780.4. As an alternative, this sequence oflayers can also be manufactured using neutral is films, as is describedin the German patent application No. 19857243.3.

FIG. 3 shows a further step of the manufacturing method for producingthe semiconductor arrangement according to the present invention. Inthis context, trenches 10 are introduced into the semiconductor wafer,which subdivide partial layer 2 into subsections, trenches 10 extendingthrough to partial layer 3. Trenches 10 can be introduced, for example,by sawing or etching. The spacing of trenches 10 is adjusted in such amanner that the wafer can subsequently be separated along the trenches,into individual chips; after the separation, each chip still has atleast one trench 10 in its interior. However, the wafer surface is firstcleaned prior to being processed further, in order to remove anyremaining particles from the surface.

In comparison with the device and method described in German Patentdocument P 4320780.4, the spacing of the saw lines is halved during thesawing-in procedure (in order to obtain two additional grooves per chip)or reduced to one third (in order to obtain four additional grooves perchip). In the present case, the spacing of the grooves is typically 1-3mm. No additional method step is necessary here, since, as is known fromGerman Patent document P 4320780.4, the sawing-in procedure is executedto lay out the chip edge, anyway. One must only set the line spacing tobe somewhat smaller during the sawing-in procedure. This does notconsiderably change the processing time of this sawing step, since thewafer handling, the alignment, and the cleaning with deionized waterdone in the automatic sawing device after the sawing-in procedure, arecarried out anyway.

After the introduction of trenches 10, a p-dopant such as Boron isintroduced into the topside. At the same time, the dopant concentrationof bottom layer 4 may be increased if so desired. P-dopant is introducedagain, using film diffusion. In this diffusion step, possible defectspresent in the silicon monocrystal in the immediate vicinity of trenches10 are repaired. The p-diffusion converts the top layer of the siliconwafer into a p-conductive region. The thickness of this p-layer isapproximately uniform over the length of the device, even in thetrenches. In FIG. 4, the resulting p-conductive layer is represented byreference numeral 20. Subsequent to the deposition of layer 20 and thepossible intensification of the doping of partial layer 4, the two sidesof the wafer are metallized so that p-conductive layer 20 is providedwith a metallic coating 22 and n-doped, third partial layer 4 isprovided with a metallic coating 21. In a further step, the wafer isdiced along separation lines 25, into a plurality of individual diodes,so that individual chips 7 are formed whose structure is described inFIGS. 1a and 1 b. Prior to sawing the wafer along separation lines 25,the wafer side having metallic coating 21, i.e. the bottom side, ispasted to a sawing sheet so that the individual chips do not fly off inan uncontrolled manner or become damaged.

The width of the saw lines during the sawing-in procedure isapproximately 40 to 150 μm, and the lengths of the chip edges are in therange of approximately 5 mm. The area of the additional saw grooves inthe interior of the individual chips only makes up a few percent of thechip surface. Of course, the method of the present invention can also beused to manufacture diodes doped in an opposite manner, i.e. diodeswhere a p-doped wafer is used as a starting point, in place of ann-doped wafer.

What is claimed is:
 1. A method for manufacturing a semiconductor chip,comprising the steps of: providing a semiconductor wafer which includesa first layer having at least two partial layers, the first partiallayer being disposed on the second partial layer, the two partial layershaving a first conductivity type, the first partial layer having a firstdopant concentration, the second partial layer having a second dopantconcentration, and the second dopant concentration being less than thefirst dopant concentration; introducing trenches into the first partiallayer, which trenches extend through the first partial layer into thesecond partial layer; introducing dopants of a second conductivity typeinto the top surface of the wafer to change the conductivity type of asection of the first partial layer and a section of the second partiallayer, whereby a second layer is formed; and depositing metalliccoatings on the top surface and the bottom surface of the wafer; andseparating the wafer along the trenches into individual chips, such thateach chip has at least one trench in its interior.
 2. The methodaccording to claim 1, further comprising the step of introducing thetrenches by sawing.
 3. The method according to claim 1, furthercomprising the step of introducing the trenches by etching.